Examining the Interaction Between Balanced Scheduling and Other Compiler Optimizations

Previous work has demonstrated that balanced scheduling is able to tolerate memory latency more effectively than traditional instruction scheduling algorithms. Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the architecture. Therefore, they cannot respond to variations in load latencies, due to cache hits/misses or congestion in the network. In contrast, balanced scheduling schedules instructions based on an estimate of the amount of instruction-level parallelism in the program. When memory latency is uncertain, balanced scheduling can hide these latencies more effectively by exploiting the available instruction-level parallelism. In this study, we examine the interactions between balanced scheduling and two compiler optimizations (loop unrolling and locality analysis) in attempts to increase the amount of parallelism in the code available to the balanced scheduler.